The present invention relates to a method and/or software for accurate capacitance acquisition generally and, more particularly, to a method and/or software for determining the capacitance of an analog/mixed signal circuit.
There are several conventional methods for CMOS cell input pin capacitance acquisition. Bipolar junction transistor BJT-CML technology requires additional special characteristics in order to determine the capacitance. The characteristics for determining the capacitance in BJT-CML technology is not clear. The conventional methods for CMOS cell capacitance acquisition is not suitable for BJT-CML cell capacitance acquisition. Currently, conventional approaches are not available for BJT-CML cell input pin capacitance acquisition.
Referring to FIG.1, a conventional circuit 10 that is used for pin capacitance acquisition is shown. The voltages across the pin capacitance are defined by the following equation EQ1:
xe2x80x83v=V(1xe2x88x92exe2x88x92t/RC)xe2x80x83xe2x80x83EQ1
By definition, the RC time constant xcfx84 is the product of R and C and is defined by the following equation EQ2:
xcfx84=RCxe2x80x83xe2x80x83EQ2
At time t=xcfx84 the voltage v is defined by the following equation EQ3:
v=V(1xe2x88x92exe2x88x92t/RC)=0.63Vxe2x80x83xe2x80x83EQ3
Using a known value of R and measuring the value of t at which the charging voltage v is 0.63 V, the pin capacitance is found by the following equation EQ4:
C=t/Rxe2x80x83xe2x80x83EQ4
Referring to FIG. 2, a graph illustrating voltage versus time of the circuit 10. The circuit 10 is sensitive to the value of R. The acquired capacitance by this method for the same pin could have 100% to 1000% variation with different values R.
Another conventional method for CMOS cell capacitance acquisition, a so-called an imaginary current method, may be defined by the following equations:
xe2x80x83V/lm=1/(WC)
W=2xcfx80f
C=lm/(2xcfx80fV) (when V=1v)
=lm/(2xcfx80f)
Using a known value of stimulus frequency f, and measuring the value of imaginary current lm, the pin capacitance can be acquired. However, the imaginary current method is very sensitive to the choice of the stimulus frequency f. The acquired capacitance by this method for the same pin could have up to 1000% variation based on different values of the stimulus frequency f.
Another conventional approach for CMOS cell capacitance acquisition, a so-called impedance method, may be defined by the following equations:
Z=(R2+(WC)xe2x88x922)xc2xd
Z2=R2+(WC)xe2x88x922(W=2xcfx80f)
C2=(1/(2xcfx80fxc2x7Z))2xc2x7((WCR)2+1)
tan xcfx86=(1/(WCR))
C=(1/(2xcfx80fxc2x7Z))xc2x7((tan xcfx86)xe2x88x922+1)xc2xd
When R is small, WCR less than  less than 1,
C=(1/(2xcfx80fxc2x7Z))
Z=Vrms/lrms
Using a known value for the stimulus frequency f, and measuring the value of Vrms and lrms, the pin capacitance can be acquired. The impedance method is also very sensitive to the choice of the stimulus frequency f. The acquired capacitance calculated by the impedance method for the same pin could have up to 1000% variation based on different values of f.
Another conventional method for CMOS cell capacitance acquisition is a so-called I/(DV/DT) method. By definition, capacitance C is defined by the following equation:
C=dQ/dV
On the other hand,
dQ=Ixc2x7dt
dQ=Cxc2x7dV=Ixc2x7dt
C=I/(dV/dt)
where V is input stimulus voltage. If a linear source voltage is used, dV/dt is a constant.
K=dV/dt
C=I/K
Take average in the range T,
(∫oTCdt)/T=((∫oTIdt)/T)xc2x7(1/K)
Avg(C)=Avg(I)/K
Measure Avg(I)xe2x86x92Avg(C)xe2x86x92C
FIG. 3 is a graph illustrating voltage as an input and current as an output, each versus time for the I/(DV/DT) method. The I/(DV/DT) method is still sensitive to input slope rate K for analog signals (BJT-CML), but may provide better tolerance (e.g., xe2x88x9250% to 50%) than other conventional methods.
None of the conventional methods described is targeted to bi-cmos technology. Additionally, the conventional methods described are not normally accurate enough for input pin capacitance acquisition.
The present invention concerns a method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance.
The objects, features and advantages of the present invention include providing a method and/or software that may allow for (i) capacitance acquisition of BJT-CML cells, and/or (ii) characterization of a BJT-CML cell library.